1. Field of the Invention
The present invention relates to a semiconductor memory device which transmits data between a memory area for storing data and outside through a data bus, and particularly relates to a semiconductor memory device having a bus configuration in which a bidirectional buffer for buffering data transmitted bidirectionally through the data bus is provided so as to shorten wiring length.
2. Description of Related Art
In recent years, as semiconductor memory devices have been highly integrated, high-speed data transfer rate has been required, and wiring length of a data bus for transmitting data of a memory cell array has been increased. Wiring capacitance and resistance of the data bus increase due to the increase in the wiring length of the data bus, thereby causing delays in data transmission, and it becomes difficult to ensure high-speed data transfer rate.
As measures against the increase in the wiring length of the data bus, a configuration has been proposed in which the data bus is divided and a bidirectional buffer is inserted therebetween (for example, see Patent References 1 and 2). By providing the bidirectional buffer, the wiring length of the data bus can be shortened while both write and read data are transmitted, and data transfer rate can be increased. Further, a memory cell array divided into a plurality of banks has been employed in recent semiconductor memory devices, and a configuration has been proposed in which the bidirectional buffer is inserted in a data bus configuration connected to the plurality of banks (for example, see Patent Reference 3).
Patent Reference 1: Laid-open Japanese Patent Publication No. 2001-102914
Patent Reference 2: Laid-open Japanese Patent Publication No. 2001-188638
Patent Reference 3: Laid-open Japanese Patent Publication No. 2003-077276
However, as the storage capacity of semiconductor memory devices has been increased, the number of wirings of the data bus is remarkably increased since a large number of lines for inputting/outputting data for the memory cell array need to be bundled, as well as the increase in the wiring length of the data bus. Thus, an area required for the wirings in a semiconductor chip increases, and consumption current inevitably increases due to the increase in the number of circuit elements in an input/output circuit. For example, if the configuration disclosed in the above conventional patent references 1 and 2 is employed, only the wiring length of the data bus can be shortened, while the number of wirings of the data bus connected through the bidirectional buffer cannot be reduced. Further, in the configuration of the above conventional patent reference 3, transmission data of the data bus connected to the plurality of banks is inputted to the bidirectional buffer, however this configuration is limited to a case where connection forms between the respective banks and the data bus are symmetrical and uniform. Therefore, it is not possible to selectively buffer the transmission data of the plurality of data buses connected to a desired bank through a desired path. Further, in a configuration where each bank is partitioned into areas, it is not assumed that there exist a bank having areas connected to the same data bus and a bank having areas connected to different data buses. As described above, when employing the data bus configuration capable of shortening the wiring length in the conventional semiconductor memory device, there is a problem that it is difficult to selectively buffer transmission data through many data buses connected to different areas in the memory cell array with various paths.